1. Field of the Invention
The present invention relates to a digital phase locked loop which can effect phase synchronization of an output signal with respect to an input signal.
2. Description of the Prior Art
Conventionally, a digital phase locked loop including a phase comparator, a low pass filter (hereinafter referred to as an LPF), and a voltage controlled oscillator (hereinafter referred to as a VCO) has been used for phase synchronization of a desired digital signal. The operation of this type of digital phase locked loop is described below.
The phase of the input signal to the phase comparator and the phase of the output signal of the VCO are compared, and the phase difference between the input signal and the VCO output signal is output from the phase comparator. This phase difference is integrated by the LPF, and a signal which oscillates at a frequency corresponding to this phase difference is obtained from the VCO and returned to the phase comparator. If the phase of the input signal has not changed, the output of the phase comparator is converged to a predetermined value after a certain period of time determined by the response characteristics, and a signal the whose phase is synchronized to the input signal is obtained as the output of the VCO. Of course, if the phase of the input signal changes, the phase of the output tracks the phase change. Such a digital phase locked loop is disclosed, for example, in Japanese Laid-Open Patent Publication No. 63-237678.
However, when this operation is actually executed by a hardware embodiment of the digital phase locked loop, the signal is delayed by the phase comparator, LPF, and VCO, and a phase error which is the sum of the delay in each circuit of the loop (in-loop delay) occurs, and the response of the digital phase locked loop deteriorates, specifically the time required to synchronize the phase of the input and output signals of the digital phase locked loop increases.